Case Study: Mobile Tranceiver
A mobile transceiver chip was designed by a fabless IC company and built on a SiGe BiCMOS process. The chip functioned properly in most aspects, except that it fell short of the RF power output specification. So the analog and RF design team rushed to debug and correct the problem.
Silicon Does Not Meet Spec
The chip was specified to produce 24dBm output power at 1.9GHz. However, the first silicon data showed the power output was half, or 3dBm less than, the target. Detailed analysis of silicon data versus simulation showed the RF power amp was weaker than expected. The power transistors dissipate heat in a concentrated area, which can cause significant temperature peaks and variations. The Gradient Virtual Thermography team was called to perform thermal simulations using HeatWave. Together, Gradient and the design team gathered the required layout, thermal model, and die material data as input for the thermal simulation.
In the original design, the transistor segments were placed in a straight line with minimum spacing. Thermal simulation showed a temperature variation (ΔT) exceeding 28°C within the chip, and 12°C within the power transistor (Fig 1). This temperature data was annotated back into the circuit simulation, showing 21dBm output power at 1.9GHz, and matching the degraded silicon performance. This confirmed that the RF power amp efficiency was degraded by the temperature variations across the transistor segments.
Eliminating the Thermal Blind Spot
In order to reclaim the power amp efficiency, the designer experimented with several different transistor segment placements, within the constraints of the existing chip layout. A version with the transistor segments placed in a diagonally staggered pattern was chosen, because the thermal simulation showed a much improved ΔT of 12°C within the chip and only 5°C within the power transistor segments (Fig 2), while minimizing the disruption to the rest of the chip layout.
Within a turnaround time of 2-3 hours, thermal simulation provided the designer with a fine-grain temperature profile of the full chip, enabling him to quickly identify a layout topology that minimized the temperature variations across the power transistors. Circuit simulation using the correct device temperatures confirmed that the new design would meet the target spec of 24dBm at 1.9GHz. This was later verified by lab measurement.
Because this chip has areas of high power density, the original circuit simulations, which assumed uniform temperature for the entire chip, produced misleading results. Precise device temperatures, computed using layout and power at the length scales of the devices, were required in order for the circuit simulation to provide relevant results.